1. Field of the Invention
The present invention relates to a Rambus application specific integrated circuit (ASIC), and more particularly, to a Rambus ASIC having a high speed testing function and a testing method thereof, in which a high speed test of 500MHz or greater is realized using a low frequency testing system.
2. Discussion of the Related Art
A conventional Rambus ASIC cell (RAC) will be described with reference to the accompanying drawings.
FIG. 1 is a schematic view illustrating a basic system of a Rambus memory. FIG. 2 is a schematic view illustrating a conventional Rambus ASIC chip and a testing circuit thereof.
As shown in FIG. 1, the basic system of a Rambus memory includes a master device, a Rambus channel, and a slave device.
In other words, the master device adopts an ASIC chip 1 constituting an ASIC core 3 and a Rambus interface 4, while the slave device adopts a Rambus DRAM (RDRAM) chip 2 constituting a Rambus interface 5 and a DRAM core 6. Data input/output between the Rambus interface 4 of the ASIC chip 1 and the Rambus interface 5 of the RDRAM chip 2 is performed at high speed, while data input/output in the ASIC core 3 is performed at low speed.
The master device has an RDRAM as a general ASIC chip and a Rambus ASIC cell (RAC) as a Rambus interface for high speed data input/output.
The RAC in the master device can perform transaction request for the RDRAM chip.
An ASIC device, a memory controller, a graphic engine, a microprocessor, and the like are examples of the master device.
The slave device always respond to request from the RAC of the master device.
The operation test of the Rambus memory system will be described below.
As shown in FIG. 2, for the operation test of the Rambus memory system, there is provided a high speed test equipment system 20 in a Rambus ASIC chip 10. The high speed test equipment system 20 drives or compares data at a speed of 500MHz or greater through each input/output (I/O) pin.
A data driver of the high speed test equipment system 20 applies a test pattern for operating an ASIC core 11 of the Rambus ASIC chip 10 to the ASIC core 11 through ASIC core input pins, and outputs data at a speed of 500MHz or greater through the RAC 12 from the ASIC core 11.
The data of 500MHz or greater is input to a comparative channel of the high speed test equipment system 20. The input data is compared with expected pattern data stored in a memory of the high speed test equipment system 20 and then tested.
High speed input/output test is performed to identify whether or not the Rambus ASIC chip 10 can output the data of 500MHz or greater through the RAC 12.
The conventional Rambus ASIC chip testing method has a problem that, to correspond to the high speed operation of the RAC of the Rambus ASIC chip, the high speed testing system is required, which increases the test cost in mass production of the Rambus ASIC chip, thereby reducing cost competition.